Fin field effect transistor including a single diffusion break with a multi-layer dummy gate

ABSTRACT

In one example, a fin field effect transistor including a single diffusion break with a multi-layer dummy gate is disclosed. One example of field effect transistor includes a first transistor array comprising a first active gate, a second transistor array comprising a second active gate, and a single diffusion break formed between the first transistor array and the second transistor array, wherein the single diffusion break comprises a dummy gate comprising multiple layers of different materials.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to complementarymetal-oxide-semiconductor technology and relates more specifically tofin field effect transistors with diffusion breaks.

BACKGROUND OF THE DISCLOSURE

Complementary metal-oxide-semiconductor (CMOS) devices often requireisolation between adjacent arrays of transistors. In fin field effecttransistor (finFET) technology, this may be accomplished by placing oneor more dummy gates between adjacent fin arrays to form what is known asa “diffusion break.” Diffusion breaks may take various forms.

In a double diffusion break (DDB), a single fin is cut, prior to gatepatterning, to form two adjacent fin arrays having a gap in between. Adummy gate is formed on each side of the gap (i.e., on the gap-end ofeach fin array). This approach thus decouples fin patterning from gateformation and allows the dummy gates to be processed in a manner similarto the active gates.

In a single diffusion break (SDB), a single fin is cut, after gatepatterning, to form two adjacent fin arrays having a gap in between. Asingle dummy gate is formed in the gap between the fin arrays. Thereduction in the number of dummy gates formed in the gap (i.e., from twoto one), relative to a DDB, allows for a denser circuit to be fabricated(as less space is consumed by dummy devices).

SUMMARY OF THE DISCLOSURE

In one example, a fin field effect transistor including a singlediffusion break with a multi-layer dummy gate is disclosed. One exampleof field effect transistor includes a first transistor array comprisinga first active gate, a second transistor array comprising a secondactive gate, and a single diffusion break formed between the firsttransistor array and the second transistor array, wherein the singlediffusion break comprises a dummy gate comprising multiple layers ofdifferent materials.

In another example, a field effect transistor includes a substrate, afirst transistor array formed on the substrate, where the firsttransistor array includes a first channel formed as a first fin and afirst active gate wrapping around the first fin, a second transistorarray formed on the substrate, where the second transistor arrayincludes a second channel formed as a second fin and a second activegate wrapping around the second fin, and a single diffusion break formedbetween the first transistor array and the second transistor array,where the single diffusion break includes a dummy gate that includes alayer of dielectric material, where a top surface of the layer of thedielectric material sits higher than top surfaces of the first fin andthe second fin, and an inactive gate formed over the layer of dielectricmaterial, where the inactive gate, the first active gate, and the secondactive gate are formed from identical materials.

In another example, a method includes forming a single diffusion breakin a channel, to break the channel into a first fin array and a secondfin array, filling a space left by the diffusion break with a dielectricmaterial, wherein a top surface of the dielectric material sits higherthan a top surface of the channel, and forming an inactive gate over thedielectric material, where forming the inactive gate includes depositinga gate dielectric layer on the dielectric material and depositing a gateconductor layer formed on the gate dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The teachings of the present disclosure can be readily understood byconsidering the following detailed description in conjunction with theaccompanying drawings, in which:

FIGS. 1A-1M illustrate top-down views of an example field effecttransistor during various stages of a fabrication process performedaccording to examples of the present disclosure;

FIGS. 2A-2M illustrate corresponding cross sectional views of theexample field effect transistor of FIGS. 1A-1M, taken along line X-X′ ofFIG. 1A;

FIGS. 3A-3M illustrate corresponding cross sectional views of theexample field effect transistor of FIGS. 1A-1M, taken along line Y-Y′ ofFIG. 1A; and

FIGS. 4A-4I illustrate corresponding cross sectional views of theexample field effect transistor of FIGS. 1E-1M, taken along line Z-Z′ ofFIG. 1.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe Figures.

DETAILED DESCRIPTION

In one example, a fin field effect transistor (finFET) including asingle diffusion break with a multi-layer dummy gate is disclosed. Asdiscussed above, a single diffusion break (SDB) between transistor finarrays in a fin field effect transistor (finFET) device allows for adenser circuit to be fabricated, relative to a double diffusion break(DDB). This is due to the fact that a SDB uses one dummy gate formed inthe gap between the fin arrays, while DDB uses two dummy gates, whichconsume more space. However, because a SDB cuts the fin and forms thedummy gate after patterning of the active gates, the dummy gate is notprocessed in the same manner as the active gates. Instead, the region inwhich the fin cut is made is filled with a dielectric material after thecut is made. Consequently, the dielectric dummy gate formed in theregion of the SDB may interfere with steps of the downstream devicefabrication process (e.g., replacement metal gate processes) and mayalso undesirably increase variability among finFET devices fabricated inthis manner.

Examples of the present disclosure provide a finFET device with a singlediffusion break (SDB) between adjacent transistor arrays, in which amulti-layer dummy gate formed in the region of the SDB comprises aninactive gate dielectric/gate conductor (e.g., high-k/metal) gate formedover a dielectric fill. Further examples of the present disclosureprovide a process for fabricating the finFET device including themulti-layer dummy gate (i.e., a dummy gate comprising multiple layers ofdifferent materials) in the region of the SDB. In one example, thedielectric fill portion of the dummy gate is recessed to a depth that islower than a depth reached by the bottom surfaces of the fins. Thisapproach allows the dummy gate to be processed in the same manner and atthe same time as the active gates. Thus, interference of the SDB withthe formation of the active gates is minimized, while device variabilityis also minimized.

FIGS. 1A-1M, 2A-2M, 3A-3M, and 4A-4I illustrate views of an examplefield effect transistor 100 during various stages of a fabricationprocess performed according to examples of the present disclosure. Inparticular, FIGS. 1A-1M illustrate top-down views of the example fieldeffect transistor 100 during various stages of the fabrication processperformed according to examples of the present disclosure. FIGS. 2A-2Millustrate corresponding cross sectional views of the example fieldeffect transistor 100 of FIGS. 1A-1M, taken along line X-X′ of FIG. 1A.FIGS. 3A-3M illustrate corresponding cross sectional views of theexample field effect transistor 100 of FIGS. 1A-1M, taken along lineY-Y′ of FIG. 1A. FIGS. 4A-4I illustrate corresponding cross sectionalviews of the example field effect transistor 100 of FIGS. 1E-1M, takenalong line Z-Z′ of FIG. 1E.

As such, when viewed in sequence, FIGS. 1A-1M, 2A-2M, 3A-3M, and 4A-4Ialso serve as a flow diagram for the fabrication process. In particular,FIGS. 1A-1M, 2A-2M, 3A-3M, and 4A-4I illustrate a process by which afinFET device including a single diffusion break may be fabricated.

Referring to FIGS. 1A, 2A, and 3A, one or more fins 104 ₁-104 ₂(hereinafter individually referred to as a “fin 104” or collectivelyreferred to as “fins 104”) may be formed on a substrate 102. Thesubstrate 102 may be formed from a semiconductor material, such as bulksilicon or silicon-on-insulator (SOI). The fins 104 may be formed fromany suitable semiconductor materials, including, but not limited to,silicon, germanium, silicon germanium, Groups III-V compoundsemiconductors (e.g., gallium arsenide), Groups II-VG compoundssemiconductors, or other like semiconductors. In some examples, the fins104 are formed from the same material as the substrate 102. For example,both the substrate 102 and the fins 104 may comprise silicon. In otherexamples, the fins 104 may be formed from a different material than thesubstrate 102. For example, the substrate may comprise silicon, whilethe fins 104 may comprise silicon germanium formed by epitaxiallygrowing silicon germanium on the silicon substrate 102 and subsequentlypatterning the epitaxial growth to form the fins 104. In anotherexample, the fins 104 may be formed by lithography, followed by etching.Other suitable techniques, such as sidewall image transfer (SIT),self-aligned double patterning (SADP), self-aligned multiple patterning(SAMP), and self-aligned quadruple patterning (SAQP) can also be used toform the fins 104.

The fins will eventually form the channels of the FET 100. In the eventthat the substrate 102 is formed from bulk silicon, an isolation (e.g.,a shallow trench isolation (STI)) area may be formed after formation ofthe fins 104. It should be noted that the fins 104 illustrated in FIGS.1A, 2A, and 3A have not yet been cut, i.e., no diffusion break has yetbeen formed. Although the example FET 100 illustrated in FIGS. 1A, 2A,and 3A includes two fins 104, any number of fins may be included,including a single fin or three or more fins. In one example where theFET 100 includes multiple fins 104, all of the fins 104 may be formed ofthe same material (e.g., all fins formed of silicon, or all fins formedof silicon germanium). In another example where the FET 100 includesmultiple fins 104, the fins 104 may be formed of different materials(e.g., some fins may be formed of silicon, while other fins may beformed of silicon germanium).

Referring to FIGS. 1B, 2B, and 3B, a plurality of dummy gates 106_(l)-106 _(n) (hereinafter individually referred to as a “dummy gate106” or collectively referred to as “dummy gates 106”) may next beformed over the fins 104, e.g., so that the dummy gates 106 wrap aroundthe fins 104 on three sides as illustrated. Each of the dummy gates 106may be formed from a single material or may be formed from layers ofdifferent materials (e.g., a gate oxide, a gate, and a gate cap, wherethe gate may be formed from amorphous silicon and the gate cap may beformed from silicon nitride or multiple layers of different dielectricmaterials such as silicon oxide and silicon nitride). Although theexample FET 100 illustrated in FIGS. 1B, 2B, and 3B includes five dummygates 106, any number of dummy gates that is three or greater may beincluded. Three dummy gates is the lower limit in this case, as thefinal FET will include at least two transistor arrays separated by adiffusion break. Each transistor array will include at least one activegate, while the diffusion break will include one inactive gate.

Referring to FIGS. 1C, 2C, and 3C, a plurality of spacers 108 ₁-108 _(n)(hereinafter individually referred to as a “spacer 108” or collectivelyreferred to as “spacers 108”) may next be formed around the dummy gates106. In one example, one spacer 108 is formed around each dummy gate106. The spacers 108 may be formed, for example, through conformaldeposition and directional etch processes. Deposition processes mayinclude, but are not limited to, atomic layer deposition (ALD) andchemical vapor deposition (CVD). Directional etch processes may include,but are not limited to, RIE. Some examples of spacer materials include,but are not limited to, silicon nitride, silicon carbide, siliconoxynitride, carbon-doped silicon oxide, silicon-carbon-nitride, boronnitride, silicon boron nitride, silicoboron carbonitride, siliconoxycarbonitride, silicon oxide, and combinations thereof. Dielectricmaterials may include low-k dielectric materials (e.g., having adielectric constant of less than approximately seven, and in one exampleapproximately five).

In addition, an epitaxial layer 110 is grown over the fins 104, betweenthe dummy gates 106. The epitaxial layer 110 will eventually form partof the source and drain regions of the FET 100. In some examples,epitaxial silicon, silicon germanium, germanium, and/or carbon-dopedsilicon can be doped during deposition (e.g., in situ doped) by addingn-type dopants (e.g., phosphorous or arsenic) or p-type dopants (e.g.,boron or gallium), depending on the type of transistor to be formed. Thedopant concentration in the source/drain regions can range from 1×10¹⁹cm⁻³ to 3×10²¹ cm⁻³, and in another example is between 2×10²⁰ cm⁻³ and3×10²¹ cm⁻³. Other doping techniques can also be used to incorporatedopants in the source/drain regions, including, but not limited to, ionimplantation, gas phase doping, plasma doping, plasma immersion ionimplantation, cluster doping, infusion doping, liquid phase doping,solid phase doping, in situ epitaxy growth, or any suitable combinationthereof.

Referring to FIGS. 1D, 2D, and 3D, an interlevel dielectric layer 112may next be formed over the substrate 102, in the spaces between thedummy gates 106, and over the epitaxial layer 110 (however, theinterlevel dielectric layer 112 is not shown over the epitaxial layer ofFIG. 1D for clarity. The interlevel dielectric layer 112 may be formedfrom a dielectric material, such as silicon nitride and/or a flowableoxide. In one example, the dielectric material is deposited over thesubstrate 102 and then planarized (e.g., down to the tops of the dummygates 106).

Referring to FIGS. 1E, 2E, 3E, and 4A, an etch mask 114 may next beformed over the dummy gates 106 and over the interlevel dielectric layer112 (the etch mask 114 is not shown in FIG. 1E or 4A for clarity). Theetch mask 114 may comprise a soft mask material (e.g., photoresist,optical planarization layer (OPL), or the like) or a hard mask material(e.g., silicon nitride or the like). The etch mask 114 may include anopening 116 over a first dummy gate 106 of the plurality of dummy gates106 (i.e., where the first dummy gate is dummy gate 106 ₃ in theillustrated example) and over portions of the interlevel dielectriclayer 112 surrounding the first dummy gate 106 ₃. The first dummy gate106 ₃ may reside over approximately the center of the fins 104 (i.e.,where the center is measured along the longest dimensions of the fins104). The first dummy gate 106 ₃ is then removed, for instance via RIE,wet etch, plasma etch, or any suitable combination thereof, as shown inFIGS. 1E, 2E, and 3E. As shown in FIG. 4A, the remaining dummy gates 106(i.e., dummy gates 106 ₁, 106 ₂, 106 ₄, and 106 _(n) in the illustratedexample) are not removed in this step, as the remaining dummy gates areprotected by the etch mask 114. Although FIG. 4A illustrates a crosssection taken along remaining dummy gate 106 ₄, the illustration is alsorepresentative of the cross sections that may be taken along the otherremaining dummy gates (i.e., dummy gates 106 ₁, 106 ₂, and 106 _(n)).

Referring to FIGS. 1F, 2F, 3F, and 4B, a single diffusion break may nextbe formed in the region of the removed first dummy gate 106 ₃. In oneexample, the single diffusion break is formed by removing portions ofthe fins 104 that are left exposed in the region below the etch maskopening 116 (i.e., below where the removed first dummy gate 106 ₃ sat).In one example, the portions of the fins 104 may be removed via a RIEprocess. In one example, the removal of the portions of the fins 104 mayalso remove a portion of the substrate 102, creating a recess 120 ₁-120₂ (hereinafter individually referred to as a “recess 120” orcollectively referred to as “recesses 120”) in the substrate 102 beloweach removed fin portion, as shown in FIGS. 2F and 3F. This results ineach fin 104 being split or broken into two separate, adjacent finarrays 126 ₁ and 126 ₂ (hereinafter individually referred to as a “finarray 126” or collectively referred to as “fin arrays 126,” and takingfin 104 ₂ of FIG. 2F as an example), where the fin arrays 126 areseparated by a recess 120. As shown in FIG. 4B, no substantial change ismade to the remaining dummy gates 106 (i.e., dummy gates 106 _(1,) 106_(2,) 106 ₄, and 106 _(n) in the illustrated example) in this step, asthe remaining dummy gates are still protected by the etch mask 114.

Referring to FIGS. 1G, 2G, 3G, and 4C, the etch mask 114 may next beremoved. Then, the single diffusion break may be filled with adielectric material 122, such as silicon nitride, silicon carbide,silicon oxynitride, carbon-doped silicon oxide, silicon-carbide-nitride,boron nitride, silicon boron nitride, silicoboron carbonitride, siliconoxycarbonitride, silicon oxide, or a combination thereof. The dielectricmaterial 122 may fill the recesses 120 and the spaces where the removedfirst dummy gate 106 ₃ sat. The dielectric material 122 may then berecessed, as shown in FIGS. 2G and 3G, so that the top surface of thedielectric material 122 is below the surface of the interleveldielectric layer 112 and the surfaces of the remaining dummy gates 106.In one example, the dielectric material 122 may be recessed to anydepth, so long as the top surface of the dielectric material 122 sitshigher than the top surfaces of the fins 104, as shown in FIG. 2G. Asshown in FIG. 4C, no substantial change is made to the remaining dummygates 106 (i.e., dummy gates 106 ₁, 106 ₂, 106 ₄, and 106 _(n) in theillustrated example) in this step.

Referring to FIGS. 1H, 2H, 3H, and 4D, the remaining dummy gates 106(i.e., dummy gates 106 ₁, 106 ₂, 106 ₄, and 106 _(n) in the illustratedexample) may next be removed. This leaves a recess that extends down tothe fins 104 in place of each of the remaining dummy gates 106. In oneexample, the remaining dummy gates 106 are removed via a RIE process.This is the start of a replacement metal gate process that will replacethe remaining dummy gates 106 with active metal gates. As shown in FIG.3H, no substantial change is made in the region of the diffusion breakin this step.

Referring to FIGS. 1I, 2I, 3I, and 4E, a gate dielectric layer 124 maynext be deposited over the substrate 102, over the fins 104, over thedielectric material 122, and over the spacers 108. The gate dielectriclayer 124 may be formed of any suitable dielectric material, including,but not limited to, silicon oxide, silicon nitride, silicon oxynitride,high-k dielectric materials, or any combination thereof. In one example,high-k dielectric materials may include, but are not limited to, metaloxides such as hafnium oxide, hafnium silicon oxide, hafnium siliconoxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide,zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide,titanium oxide, barium strontium titanium oxide, barium titanium oxide,strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandiumtantalum oxide, and lead zinc niobate. The high-k dielectric materialsmay further include dopants, including, but not limited to, lanthanum,aluminum, and magnesium. The gate dielectric layer 124 may be formed byany suitable process or combination of processes, including, but notlimited to, thermal oxidation, chemical oxidation, thermal nitridation,plasma oxidation, plasma nitridation, atomic layer deposition, chemicalvapor deposition, and the like. In some examples the thickness of thegate dielectric layer 124 is between one and five nanometers, althoughthicknesses outside of this range are also possible.

Next, gate conductor layer 128 may be deposited over the gate dielectriclayer 124 and planarized (e.g., by chemical mechanical planarization)down to the surface of the interlevel dielectric layer 112. The gateconductor layer 128 may be formed of any suitable conducting material,including, but not limited to, doped polycrystalline or amorphoussilicon, germanium, silicon germanium, a metal (e.g., tungsten,titanium, tantalum, ruthenium, hafnium, zirconium, cobalt, nickel,copper, aluminum, platinum, tin, silver, or gold), a conducting metalliccompound material (e.g., tantalum nitride, titanium nitride, tantalumcarbide, titanium carbide, titanium aluminum carbide, tungsten silicide,tungsten nitride, ruthenium oxide, cobalt silicide, or nickel silicide),a transition metal aluminide (Ti₃AL or zirconium aluminum), tantalumcarbide, tantalum magnesium carbide, carbon nanotube, conductive carbon,graphene, or a combination thereof. The conducting material may furthercomprise dopants that are incorporated during or after deposition. Thegate conductor layer 128 may be formed by any suitable process orcombination of processes, including, but not limited to, atomic layerdeposition, chemical vapor deposition, physical vapor deposition,sputtering, plating, evaporation, ion beam deposition, electron beamdeposition, laser-assisted deposition, chemical solution deposition, ora combination thereof.

In some examples, a work function setting layer (not shown) may bepositioned between the date dielectric layer 124 and the gate conductorlayer 128. The work function setting layer may be formed of a workfunction metal (WFM), which may be any suitable metal, including, butnot limited to, a nitride (e.g., titanium nitride, titanium aluminumnitride, hafnium nitride, hafnium silicon nitride, tantalum nitride,tantalum silicon nitride, tungsten nitride, molybdenum nitride, orniobium nitride), a carbide (e.g., titanium carbide, titanium aluminumcarbide, tantalum carbide, or hafnium carbide), or combinations thereof.In some examples, a conductive material or a combination of conductivematerials may serve as both the gate conductor layer 128 and the workfunction setting layer. The work function setting layer may be formed byany suitable process or combination of processes, including, but notlimited to, atomic layer deposition, chemical vapor deposition, physicalvapor deposition, sputtering, plating, evaporation, ion beam deposition,electron beam deposition, laser-assisted deposition, chemical solutiondeposition, or a combination thereof.

Notably, the gate dielectric layer 124 and the gate conductor layer 128are both formed in the region of the diffusion break (i.e., where thefirst dummy gate 106 ₃ originally sat), as well as in the regions wherethe remaining dummy gates 106 originally sat. In the region of thediffusion break, the gate dielectric layer 124 and the gate conductorlayer 128 form an inactive gate above the dielectric material 122;collectively the dielectric material 122 and the inactive gate formedabove the dielectric material form a dummy gate. However, in the regionswhere the remaining dummy gates 106 originally sat, the gate dielectriclayer 124 and the gate conductor layer 128 form active gates. Thus, thedielectric material 122 in the region of the diffusion break does notinterfere with the replacement metal gate process for the active gates.

Referring to FIGS. 1J, 2J, 3J, and 4F, the gate conductor layer 128 maynext be recessed in all gates (i.e., including the inactive gate in thediffusion break and all active gates in the fin arrays 126. In oneexample, because the inactive gate in the diffusion break also includesthe gate conductor layer 128, this step may be performed at once for allof the gates, so that all of the gates are recessed uniformly (e.g., asshown in FIGS. 3J and 4F).

Referring to FIGS. 1K, 2K, 3K, and 4G, a gate cap layer 130 may next bedeposited over the gate conductor layer 128 that was just recessed. Thegate cap layer 130 may be formed, for example, from a dielectricmaterial such as silicon nitride. In one example, the gate cap layer 130is deposited and then planarized down to the level of the interleveldielectric layer 112. Again, because the inactive gate in the diffusionbreak also includes a gate conductor layer 128 that is recesseduniformly with the gate conductor layer 128 of the active gates, thisstep may be performed at once for all of the gates, so that all of thegates are capped uniformly (e.g., as shown in FIGS. 3K and 4G).

Referring to FIGS. 1L, 2L, 3L, and 4H, source and drain contacts 132 maynext be formed over the epitaxial layer 110. In one example, formationof the source and drain contacts comprises depositing a conductivematerial over the epitaxial layer 110, in the spaces between the gatesand at the ends of the FET 100, as shown in FIGS. 1L and 2L. Inparticular, a first set of source and drain contacts may be formed inthe spaces between the active gates of the first fin array 126 ₁, whilea second set of source and drain contacts may be formed in the spacesbetween the active gates of the second fin array 126 ₂. The source anddrain contacts 132 may be formed of any suitable conducting material,including, but not limited to, tungsten, aluminum, copper, cobalt,nickel, titanium, or a combination thereof. The source and draincontacts 132 may further include a barrier layer formed, for example, oftitanium nitride, tantalum nitride, hafnium nitride, niobium nitride,tungsten nitride, carbon nanotubes, graphene, or a combination thereof.The barrier layer may minimize diffusion and/or alloying of theconducting material with the top source/drain contact material and/oranode/cathode material. In various examples, the barrier layer may beconformally deposited by atomic layer deposition, chemical vapordeposition, metal organic chemical vapor deposition, plasma enhancedchemical vapor deposition, or a combination thereof. In variousexamples, the conducting material can be deposited by atomic layerdeposition, chemical vapor deposition, physical vapor deposition, or acombination thereof to form the source/drain contacts 132.

The resulting FET 100, as illustrated in 1M, 2M, 3M, and 4I thereforeincludes a single diffusion break 134 between the adjacent fin arrays126 (e.g., first fin array 126 ₁ and second fin array 126 ₂) thatsupport the active gates 136 ₁-136 _(m) (hereinafter individuallyreferred to as an “active gate 136” or collectively referred to as“active gates 136”). The single diffusion break 134 is recessed to adepth that is lower than the bottom surfaces of the fins (e.g.,partially into the substrate 102 supporting the fins). A dummy gate 138,comprising a lower layer of a dielectric fill (i.e., dielectric material122) and an upper layer of an inactive gate 140 (comprising gatedielectric layer 124, gate conductor layer 128, and gate cap layer 130),is formed in the recess. This stands in contrast to conventional singlediffusion break fabrication processes, which form the dummy gate in thediffusion break entirely from a dielectric material. As discussed above,separate fabrication of the dummy gate and the active gates in theconventional manner may interfere with subsequent downstream processingof the active gates. However, including the upper layer of the inactivegate 140 in the dummy gate 138 of the disclosed FET 100 allows the dummygate 138 and the active gates 136 to be fabricated simultaneously (e.g.,processed in the same way at the same time) during downstreamprocessing, in a common series of processing steps. This, in turn,minimizes interference with formation of the active gates 136. Thus,variability among FET devices fabricated according to the disclosedprocess is minimized.

Although various embodiments which incorporate the teachings of thepresent invention have been shown and described in detail herein, thoseskilled in the art can readily devise many other varied embodiments thatstill incorporate these teachings.

What is claimed is:
 1. A method comprising: forming a first array offins and a second array of fins on a substrate; forming an array of gatestructures perpendicular to and wrapping portions of both the firstarray of fins and the second array of fins; and forming a singledielectric material directly below one gate structure, the singledielectric material isolates the first array of fins from the secondarray of fins, wherein sidewalls of the single dielectric material arecoplanar with sidewalls of the one gate structure.
 2. The method ofclaim 1, wherein a portion of the single dielectric material extendsdownward into the substrate below the first array of fins and below thesecond array of fins, wherein the portion of the single dielectricmaterial corresponds with a size and a location of opposing fins fromthe first array of fins and below the second array of fins.
 3. Themethod of claim 1, wherein upper most surfaces of a gate cap, a gatedielectric, and a sidewall spacer are substantially flush with oneanother.
 4. The method of claim 1, wherein upper most surfaces of boththe single dielectric material and adjacent epitaxial source drainregions are above a lower most surface of a sidewall spacer separatingthe single dielectric material from the adjacent epitaxial source drainregions.
 5. The method of claim 1, wherein a vertical sidewall of a gatedielectric layer of the one gate structure is in direct contact with asidewall spacer, the sidewall spacer is in direct contact with avertical sidewall of an adjacent epitaxial source drain region, and abottom most surface of the sidewall spacer is below an upper mostsurface of the adjacent epitaxial source drain regions.
 6. The method ofclaim 1, wherein each gate of the array of gate structures comprises: agate dielectric layer; a gate conductor layer formed over the gatedielectric layer; and a gate cap layer formed over the gate conductorlayer.
 7. The method of claim 1, wherein sidewalls of the singledielectric material are coplanar with sidewalls of the one gatestructure.
 8. A method comprising: forming a first transistor arraycomprising a first active gate; forming a second transistor arraycomprising a second active gate; and forming a single diffusion breakformed between the first transistor array and the second transistorarray, wherein the single diffusion break comprises a dummy gatecomprising a layer of dielectric material, and an inactive gatestructure formed over the layer of dielectric material, wherein alateral width of the layer of dielectric material is substantially equalto a lateral width of the inactive gate structure, wherein a sidewallspacer directly contacts and separates the layer of dielectric materialfrom an adjacent epitaxial source drain region.
 9. The method of claim8, wherein the first transistor array further comprises: a first channelformed as a first fin, where the first active gate wraps around thefirst fin, and wherein the second transistor array further comprises: asecond channel formed as a second fin, where the second active gatewraps around the second fin.
 10. The method of claim 8, wherein uppermost surfaces of both the layer of dielectric material and the adjacentepitaxial source drain region are above a lower most surface of thesidewall spacer.
 11. The method of claim 9, wherein a top surface of thelayer of the dielectric material sits higher than top surfaces of thefirst fin and the second fin.
 12. The method of claim 8, wherein theinactive gate, the first active gate, and the second active gate areformed from identical materials.
 13. The method of claim 12, wherein theidentical materials comprise: a gate dielectric layer; a gate conductorlayer formed over the gate dielectric layer; and a gate cap layer formedover the gate conductor layer.
 14. The method of claim 10, furthercomprising: a semiconductor substrate on which the first transistorarray, the second transistor array, and the single diffusion break areformed, wherein the layer of the dielectric material fills a recessformed in a portion of the semiconductor substrate, the recesscorresponding with a size and a location of a first fin and a secondfin.
 15. The method of claim 14, wherein a depth of the recess is lowerthan a depth to which bottom surfaces of the first transistor array andthe second transistor array reach.
 16. The method of claim 8, whereinsidewalls of the single dielectric material are coplanar with sidewallsof the one gate structure.
 17. A method comprising: forming a singlediffusion break in a channel, to break the channel into a first finarray and a second fin array; wherein forming the single diffusion breakcomprises: forming a plurality of dummy gates that wrap around thechannel; and removing a first dummy gate of the plurality of dummygates; and removing a portion of the channel residing below the firstdummy gate; filling a space left by the diffusion break with adielectric material, wherein a top surface of the dielectric materialsits higher than a top surface of the channel; and forming an inactivegate over the dielectric material, wherein forming the inactive gatecomprises: depositing a gate dielectric layer on the dielectricmaterial; and depositing a gate conductor layer formed on the gatedielectric layer, forming a first active gate that wraps around thefirst fin array; and forming a second active gate that wraps around thesecond fin array, wherein the first active gate, the second active gate,and the inactive gate are formed simultaneously during depositing thegate dielectric layer and the depositing the gate conductor layer. 18.The method of claim 17, further comprising: forming a recess in aportion of the substrate residing below the portion of the channel thatwas removed.
 19. The method of claim 18, wherein a depth of the recessis lower than a depth to which bottom surfaces of the first transistorarray and the second transistor array reach.
 20. The method of claim 17,wherein the forming the first active gate and the forming the secondactive gate comprises, prior to the depositing the gate dielectric layerand the depositing the gate conductor layer: removing remaining dummygates of the plurality of dummy gates, after removing the first dummygate and after filling the space left by the diffusion break with thedielectric material, wherein the gate dielectric layer and the gateconductor layer are deposited in spaces left by removing the remainingdummy gates.